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L1[02:22:10] <liach> @CovertJaguar It seems railcraft tile entities get cme frequently in singleplayer debug worlds (mainly actuator) and we need a fix
L2[02:41:57] <Cream Tea> I tried the interlock thing for that problem
L3[02:42:12] <Cream Tea> I want to solve this just for the fact that I don't like unsolved puzzles ??
L4[02:42:24] <Cream Tea> For anyone who didn't see:
L5[02:42:25] <Cream Tea> https://cdn.discordapp.com/attachments/225184360049934336/408696809372778496/2018-02-01_18.54.33.png
L6[02:42:38] <Cream Tea> Obviously it's short for demonstration purposes
L7[02:42:45] <Cream Tea> but supposing the length of single track was longer
L8[02:42:55] <Cream Tea> trains from the left and right should have priority,
L9[02:43:09] <Cream Tea> but when a train from the left goes past it should let the train from the branch join
L10[02:43:22] <Cream Tea> if the aspect is yellow, otherwise it could be waiting there forever.
L11[02:43:42] <Cream Tea> The interlock boxes did what they were supposed to do, however I don't think it's what I want them to do.
L12[02:44:10] <Cream Tea> The interlocks only allow one at a time, whereas here it almost works, it's just when a train goes to the left it lets both the branch and the one on the right collide.
L13[02:44:17] <Cream Tea> But then when there isn't a train on the branch
L14[02:44:22] <Cream Tea> it still makes the right red sometimes.
L15[02:44:38] <Cream Tea> If there isn't a train on the branch it should be allowed to let one from the right go through.
L16[02:44:41] <Cream Tea> Any ideas?
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L18[02:48:45] <Cream Tea> I did manage to get the interlocks working but it doesn't give the required result.
L19[02:48:56] <Cream Tea> Not sure if what I said is too confusing ??
L20[02:49:12] <Cream Tea> basically the two double sections get priority,
L21[02:49:22] <Cream Tea> but the branch should still be able to come on if the it's yellow
L22[02:49:27] <Cream Tea> like heading to the right
L23[02:51:29] <liach> i think you should just ask covertjaguar
L24[02:51:44] <liach> anyways nothing is really going on in railcraft
L25[02:51:52] <CovertJaguar> hmm
L26[02:53:18] <CovertJaguar> don't know what would cause CMEs
L27[02:53:24] <Hanakocz> @Cream Tea you probably should make those pictures with aura goggles equipped, so the connections are visible
L28[02:53:39] <Cream Tea> yeah
L29[02:53:45] <Cream Tea> I should
L30[02:55:22] <liach> @CovertJaguar I think it is client thread looking up tile entities while server thread loads them
L31[02:55:57] <Hanakocz> you know what might be a problem? you just send the "go" signal to two parts at once, but then both trains start going on same time. You need to postpone one signal by a little (repeaters?)
L32[02:56:07] <Cream Tea> yeah probably
L33[02:56:12] <Cream Tea> hmm
L34[02:56:16] <Cream Tea> put then it will still do it
L35[02:56:17] <CovertJaguar> eh? would that cause a CME? if so should be easy fix, just check if chunk is loaded before looking them up
L36[02:56:28] <Cream Tea> actually no they're the same length
L37[02:56:33] <Cream Tea> from the block signals, perhaps.
L38[02:58:08] <CovertJaguar> I think I'd need to see a pick with interlocks and links
L39[02:58:23] <Hanakocz> tea, you need to postpone it by the amount of time that is needed if first train sent foward, and if yes, it will block signal to the second line
L40[03:00:52] <LizzyTheSiren> i'm not sure what CME means in this context, the only thing that is coming to mind is coronal mass ejections
L41[03:06:02] <Cream Tea> i don't even need the problem solved for anything
L42[03:06:08] <Cream Tea> but it's one i've been trying to figure out for ages
L43[03:06:12] <Cream Tea> and I hate unsolved problems
L44[03:06:40] <Cream Tea> i'll get a picture with the goggles
L45[03:07:04] <liach> @LizzyTheSiren I mean concurrentmodificationexception
L46[03:09:31] <LizzyTheSiren> ah
L47[03:09:33] <Cream Tea> http://tinyurl.com/ycpoxxag
L48[03:09:35] <Cream Tea> Here
L49[03:09:39] <Cream Tea> and a closeup:
L50[03:10:03] <Cream Tea> http://tinyurl.com/ya2lvuqv
L51[03:10:27] <Cream Tea> The interlock is letting one out at a time
L52[03:10:31] <Cream Tea> BUT
L53[03:10:35] <Cream Tea> as you can see, there is no traffic on the branch
L54[03:10:42] <Cream Tea> but it still holds the main line
L55[03:15:05] <Cream Tea> http://tinyurl.com/y9qlefq8
L56[03:15:14] <Cream Tea> for some reason it didn't show it but that receiver is linked to that end
L57[03:16:14] <liach> This reminds me of https://github.com/Railcraft/Railcraft/issues/1351
L58[03:17:45] <CovertJaguar> you have a few extra parts in your setup I think
L59[03:18:29] <Cream Tea> http://tinyurl.com/ybcrk8oh
L60[03:18:34] <Cream Tea> This bit is a receiver and a controller
L61[03:18:38] <Cream Tea> not influenced by the interlock
L62[03:18:44] <Cream Tea> because here the trains are going out
L63[03:18:52] <Cream Tea> I didn't think it needed it
L64[03:18:55] <Cream Tea> and trains can't come in
L65[03:19:01] <Cream Tea> because if it's yellow or red it will stop
L66[03:19:25] <Cream Tea> and the switch http://tinyurl.com/ybtg4gfs
L67[03:19:32] <Cream Tea> doesn't go that way
L68[03:20:17] <CovertJaguar> you signals are also really far away from the block boundaries (the locking tracks)
L69[03:20:34] <Cream Tea> They are all equal lengths away
L70[03:20:40] <Cream Tea> I guess that would affect it though.
L71[03:20:59] <CovertJaguar> equal yes, but the trains can move into the block for a while before the interlock knows about it
L72[03:21:12] <Cream Tea> yeah
L73[03:21:18] <Cream Tea> but even without that issue
L74[03:21:22] <Cream Tea> when the train uh goes out
L75[03:21:24] <Cream Tea> let me draw it
L76[03:22:59] <CovertJaguar> you probably also need three lanes on the interlock, instead of using the interlock override for the third input
L77[03:23:41] <Cream Tea> http://tinyurl.com/ychlw6he
L78[03:23:50] <Cream Tea> the red bit is when a train has passed
L79[03:24:08] <Cream Tea> If they both go green at the same time, because it thinks the line is clear
L80[03:24:15] <Cream Tea> then they will collide
L81[03:24:23] <Cream Tea> because there isn't like a priority system
L82[03:24:36] <Cream Tea> I don't know how to do it
L83[03:24:41] <Forecaster> I think you just need to put a one-way delay on the bottom one
L84[03:24:56] <Cream Tea> how do I do tat? >.<
L85[03:24:59] <Cream Tea> Just repeaterS?
L86[03:25:03] <Forecaster> uh no
L87[03:25:21] <Forecaster> I mean, a circuit that delays it turning on-but no delay turning off
L88[03:25:33] <Cream Tea> That's a good idea
L89[03:25:36] <Cream Tea> don't think I've done that before
L90[03:25:37] <Cream Tea> :x
L91[03:25:59] <Forecaster> I've designed a vanilla circuit for that, but I don't remember it off the top of my head
L92[03:26:24] <Cream Tea> I was thinking perhaps I should use the capacitor block
L93[03:26:28] <Cream Tea> but that only makes it stay
L94[03:26:31] <Cream Tea> it doesn't delay
L95[03:26:59] <CovertJaguar> they shouldn't both go green ever hmm
L96[03:27:03] <Cream Tea> ohh
L97[03:27:08] <Cream Tea> that's without the interlock
L98[03:27:18] <Cream Tea> sorry I should have use the previous screenshot
L99[03:27:23] <Cream Tea> with the interlock it's a worse problem
L100[03:27:53] <Hanakocz> wish we could have some better system, like factorio has or something...but that would mean to store somewhere the array of blocks and check on whole array....rip cpu
L101[03:28:18] <CovertJaguar> well if you are using the interlock, it should have three lanes, you only have two, that might fix those issues
L102[03:29:06] <Cream Tea> http://tinyurl.com/ybknm9oa
L103[03:29:06] <CovertJaguar> you also have an extra controller/receiver pair on each lane that is mostly redundant
L104[03:29:12] <Cream Tea> That screenshot is with the interlock
L105[03:29:24] <Cream Tea> Because it only lets one aspect through
L106[03:29:41] <Forecaster> http://tinyurl.com/y9qsd8fk
L107[03:29:43] <Forecaster> this is it
L108[03:29:48] <CovertJaguar> you also need the inputs to be coming from detectors that report whether a train is currently waiting
L109[03:30:05] <CovertJaguar> atm your inputs are always green
L110[03:30:07] <Cream Tea> I had thought about using three interlocks, but then if it's only going one direction I didn't think it would be necessary
L111[03:30:26] <Cream Tea> wait, am I not supposed to link the signals directly to the interlocks?
L112[03:30:36] <CovertJaguar> you can
L113[03:30:46] <CovertJaguar> but your output side has an extra link
L114[03:30:57] <CovertJaguar> you can link directly to the recievers on the locking tracks
L115[03:31:00] <CovertJaguar> from the interlock block
L116[03:31:30] <Cream Tea> ah okay
L117[03:31:38] <Cream Tea> http://tinyurl.com/yb5rgryw
L118[03:31:58] <Cream Tea> and if I put a detector under the locking track
L119[03:32:00] <CovertJaguar> the signal should probably be hooked to the override receiver on the end
L120[03:32:16] <CovertJaguar> but I can't say that with 100% certaintity
L121[03:32:29] <Cream Tea> worth a try
L122[03:33:15] <CovertJaguar> input should be: "is a train waiting", and the outputs directly to the locking track release
L123[03:33:20] <CovertJaguar> then it should work
L124[03:33:35] <Cream Tea> I shall try that
L125[03:33:40] <Cream Tea> let me check
L126[03:45:44] <Cream Tea> Would a token system be more useful?
L127[03:46:17] <Forecaster> maybe
L128[04:14:54] <Cream Tea> I think I got it working http://tinyurl.com/yccohkfj
L129[04:14:56] <Cream Tea> Must be tthe most complex layout ever
L130[04:15:00] <Cream Tea> just for the most simplest task
L131[04:16:41] <Forecaster> that looks like you may have over-complicated it :P
L132[04:19:37] <Cream Tea> probably
L133[04:20:55] <Cream Tea> ima try a different way
L134[04:40:02] <Forecaster> try the delaying circuit
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L137[06:08:37] <Natesky9> Oh!
L138[06:08:38] <Natesky9> I know
L139[06:09:13] <Natesky9> I had to invert the signal from a train on each "waiting" line
L140[06:09:20] <Natesky9> exactly because of that reason
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L142[06:16:51] <Resuz> What are these lasers?
L143[06:17:14] <Natesky9> They're the signals as seen from the trackman's goggles
L144[06:17:36] <Natesky9> If you hold the goggles in-hand, and right click them, it cycles the mode they are in
L145[06:20:19] <Hanakocz> it basically visualizes the connections of signals
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L147[07:23:42] <Cream Tea> aaaaaaa
L148[07:23:51] <Cream Tea> Okay I'll try the delaying circuit.
L149[07:24:09] <Cream Tea> Is there not a better way to delay a signal?
L150[07:24:19] <Cream Tea> I guess I have to use redstone unless I use computercraft
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L152[07:31:12] <Forecaster> pretty much
L153[07:31:13] <Forecaster> :P
L154[07:31:39] <Forecaster> .s/computercraft/OpenComputers/
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L158[09:25:42] <LizzyTheSiren> ^
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L166[12:54:24] <travis-ci> Railcraft/Railcraft#943 (liach-1.10.2 - 403460c : liach): The build passed.
L167[12:54:24] <travis-ci> Change view : https://github.com/Railcraft/Railcraft/compare/8ebc9043ee97...403460c7ae72
L168[12:54:24] <travis-ci> Build details : https://travis-ci.org/Railcraft/Railcraft/builds/336684652
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